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EMIF10-COM01F2
10-line IPADTM, EMI filter including ESD protection
Features

EMI symmetrical (I/O) low-pass filter Lead free package Very low PCB space consuming: < 6 mm2 Very thin package: 0.65 mm High efficiency in ESD suppression on both input & output pins High reliability offered by monolithic integration Figure 1. Flip Chip (25 bumps) Pin configuration (bump side)
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I5
Complies with the following standard:
IEC 61000-4-2 level 4 - 15 kV (air discharge) - 8 kV (contact discharge)
4
I4
3
I3
2
I2
1
I1
A B C D E
Applications
EMI filtering and ESD protection for:

I10
I9
I8
I7
I6
GND
GND
GND
GND
GND
Computers and printers Communication systems Mobile phones Figure 2.
010
09
08
07
06
05
04
03
02
01
Description
The EMIF10-COM01F2 is a highly integrated device designed to suppress EMI / RFI noise in all systems subjected to electromagnetic interferences. The EMIF10 Flip-Chip packaging means the package size is equal to the die size. Additionally, this filter includes an ESD protection circuitry which prevents damage to the application when subjected to ESD surges up to 15 kV.
Basic cell configuration
Low-pass Filter
Input
Output
RI/O = 200 Cline = 45 pF
TM: IPAD is a trademark of STMicroelectronics.
April 2008
Rev 5
1/7
www.st.com 7
Characteristics
EMIF10-COM01F2
1
Characteristics
Table 1.
Symbol VPP Tj Top Tstg
Absolute ratings (Tamb = 25 C)
Parameter and test conditions ESD discharge IEC61000-4-2, air discharge ESD discharge IEC61000-4-2, contact discharge Junction temperature Operating temperature range Storage temperature range Value 15 8 125 - 40 to + 85 - 55 to + 150 Unit kV C C C
Table 2.
Symbol VBR IRM VRM VCL Rd IPP RI/O Cline Symbol VBR IRM Rd RI/O Cline tLH
Electrical characteristics (Tamb = 25 C)
Parameter Breakdown voltage Leakage current @ VRM Stand-off voltage Clamping voltage Dynamic impedance Peak pulse current Resistance between Input and Output Input capacitance per line Test conditions IR = 1 mA VRM = 3 V per line IPP = 10 A, tp = 2.5 s 180 At 0 V bias Vinput = 2.8 V Rload = 100 k 1 200 45 220 50 25 Min. 6 Typ. 8
slope : 1 / R d IPP VCL VBR VRM IRM IR
I
V
Max. 10 500
Unit V nA pF ns
Figure 3.
0.00 dB -10.00 -20.00
S21(db) attenuation measurement(1)
Figure 4.
0.00 dB -10.00
Analog crosstalk
-20.00
-30.00
-40.00
-50.00
-30.00 -40.00 -50.00 100.0k 1.0M 10.0M 100.0M f/Hz 1.0G
-60.00
-70.00
-80.00
-90.00
-100.00 100.0k 1.0M Xtalk 1/2 10.0M f/Hz 100.0M 1.0G
1. Spikes at high frequencies are induced by the PCB layout
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EMIF10-COM01F2
Characteristics
Figure 5.
Figure 6. ESD response to IEC 61000-4-2 (+15 kV air discharge) on one input (Vin) and on one output (Vout)
ESD response to IEC 61000-4-2 (-15 kV air discharge) on one input (Vin) and on one output (Vout)
V(in1)
V(in1)
V(out1) V(out1)
Figure 7.
Rise time measurement
EMIF10-COM01F2
In
Out
Square signal Generator Vc = 2.8V
Vin
100k
Vout
Figure 8.
Capacitance versus reverse applied voltage
C(pF) 50 F=1MHz Vosc=30mV 40
30
20
10 0 1 2 VR(V) 3 4 5
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Application information
EMIF10-COM01F2
2
Application information
Figure 9.
in MODEL = demif10
Aplac model
200R out MODEL = demif10
Demif10 model BV = 7 IBV = 1m CJO = 25p M = 0.3333 RS = 1 VJ = 0.6 TT = 100n
sub
2.1
PCB grounding recommendations
In order to ensure a good efficiency in terms of ESD protection and filtering behavior, we recommend to implement microvias (100 m dia.) between the GND bumps and the GND layer. GND bumps can be connected together in PCB layer 1, and in addition, if possible, use through hole vias (200 m dia.) in both sides of filter to improve contact to GND (layer). This layout will minimize the distance to the ground and thus parasitic inductances. In addition, we recommend to have GND plane wherever possible.
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Ordering information scheme
Figure 10. Ordering information scheme
EMIF
EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10(pF) or 3 letters = application 2 digits = version Package F = Flip Chip x = 2: Lead-free, pitch = 500 m, bump = 315 m
yy
-
xxx zz
Fx
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EMIF10-COM01F2
Package information
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Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Figure 11. Flip Chip package dimensions
500 m 50 315 m 50
500 m 50
650 m 65
2.39 mm 30 m
Figure 12. Footprint recommendations
Figure 13. Marking
Copper pad Diameter: 250 m recommended, 300 m max
2.39 mm 30 m
Dot, ST logo xx = marking z = manufacturing location yww = datecode (y = year ww = week)
E
Solder stencil opening: 330 m
Solder mask opening recommendation: 340 m min for 300 m copper pad diameter
xxz y ww
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Ordering information Figure 14. Flip Chip tape and reel specification
Dot identifying Pin A1 location 4 0.1 O 1.5 0.1
EMIF10-COM01F2
1.75 0.1 3.5 0.1
2.6
0.73 0.05
All dimensions in mm
8 0.3
STE
STE
STE
xxz yww
User direction of unreeling
xxz yww
xxz yww
4 0.1
2.6
5
Ordering information
Table 3. Ordering information
Marking FE Package Flip Chip Weight 8.3 mg Base qty 5000 Delivery mode Tape and reel
Order code EMIF10-COM01F2
Note:
More information is available in the application notes: AN1235: "Flip Chip: Package description and recommendations for use" AN1751: "EMI Filters: Recommendations and measurements"
6
Revision history
Table 4.
Date 14-Dec-2004 08-Apr-2005 19-Oct-2005 03-Apr-2006
Document revision history
Revision 1 2 3 4 First issue. Die shrink. Replaced Figures 3 and 13. Added ECOPACK statement. Reformatted to current standard. Pin identification in Figure 1 updated. Updated ECOPACK statement. Updated Figure 10, Figure 11 and Figure 14. Reformatted to current standards. Description of changes
17-Apr-2008
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EMIF10-COM01F2
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